Chip startup raises $135M betting memory, not compute, is AI's biggest bottleneck

Every time you ask ChatGPT a question, your request sets off a data relay race. Information moves out of memory, passes through the CPU for preprocessing, travels to the GPU for intensive computation, and then returns — and that entire loop repeats for every single word the AI generates.

This bottleneck is structural — it forces every request to travel through some of the most expensive and power-hungry chips in the industry. That inefficiency is exactly what XCENA, a startup with offices in South Korea and the U.S., is working to solve. The four-year-old company has built a chip that puts processing power much closer to DRAM — the fast, temporary memory chips that hold data the processor is actively using — allowing routine data tasks to be handled right next to memory, without the expensive round trips between CPUs, GPUs, and memory.

If the technology works at scale, the impact on AI infrastructure costs could be substantial — which explains the strong investor interest. XCENA just raised $135 million in a Series B round at a $570 million valuation, bringing its total funding to $185 million.

XCENA CEO Jin Kim co-founded the company in 2022 alongside CTO Dohun Kim and CPO Harry Juhyun Kim. All three are veterans of Samsung and SK Hynix, the memory giants that supply the chips powering Nvidia's GPUs. "CPUs and GPUs have both gotten smarter over the decades. Memory never did. XCENA wants to change that," Kim said in an interview with TechCrunch. "The recent rise in memory prices and related stocks points to a broader shift in AI infrastructure toward memory-centric architectures," he added. (This month, Samsung, SK Hynix, and Micron — the three companies that dominate the global memory chip market — each crossed a trillion-dollar valuation for the first time.)

Kim says XCENA is betting its business on the idea that "inference isn't just a compute problem anymore; it's increasingly a memory scaling problem."

XCENA's chip, the MX1, connects to the CPU through CXL (Compute Express Link) — essentially a dedicated express lane between the processor and memory — processing data before it ever needs to leave the memory module. It brings computation to the data, not the other way around. The company says what used to take 10 servers could potentially run on just one.

"While GPUs excel at matrix multiplication — the heavy math behind AI model training — much of the surrounding data work, including preprocessing, KV cache management (the system that stores previous conversation context so the model doesn't have to reprocess it), and data caching, still runs on CPUs. Our chip handles those tasks directly within the memory module itself," Kim said.

Demand for memory solutions has surged since the second half of last year, and the company believes the timing is working in its favor.

Discussions with several global memory vendors are still in the early stages, though Kim declined to name them. The company's ideal customers are hyperscalers spending tens of billions of dollars each year on AI infrastructure, where even a small gain in memory efficiency can translate into hundreds of millions in savings.

The MX1 is still a prototype. Mass production chips are scheduled to come off Samsung's foundry lines by the end of 2026, with the company expecting to start generating revenue in 2027.

While neural processing unit (NPU) makers are competing to challenge Nvidia for training workloads, XCENA is targeting the memory-intensive layer that underpins everything else.

XCENA's closest competitors include Astera Labs and Marvell, both Nasdaq-listed companies working on next-generation memory connectivity. Kim says Marvell is a large, established player already active in the same space, but the key difference comes down to intellectual property. "We have thousands of cores," Kim said. Based on public specs, Marvell's approach relies on a handful of general-purpose cores by comparison.

These cores are built on RISC-V — an open-source chip design blueprint — and optimized specifically for data processing, with each core deliberately kept small and efficient. Beyond the cores themselves, XCENA designs its own internal memory hierarchy, interconnect bus, and DRAM controller — a level of vertical integration that most chip companies, including larger rivals, typically outsource.

Seoul-based VC firms Altinum and IMM Investment co-led the Series B round, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company, which has more than 90 employees across offices in Pangyo, a tech hub outside Seoul, and Sunnyvale, is also in conversations with international investors about additional funding.